DS90UH927Q-Q1 Datasheet, PDF (3/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

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5 Pin Configuration and Functions
DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
RTA Package
40-Pin WQFN With Exposed Thermal Pad
Top View
RxIN1- 31
RxIN1+ 32
RxIN2- 33
RxIN2+ 34
RxCLKIN- 35
RxCLKIN+ 36
RxIN3- 37
RxIN3+ 38
GPIO0 39
GPIO1 40
DS90UH927Q-Q1
TOP VIEW
DAP = GND
20 CMF
19 VDD33_A
18 PDB
17 DOUT+
16 DOUT-
15 RES1
14 CAPHS12
13 RES0
12 CAPP12
11 IDx
Pin Functions
NAME
PIN
NO.
I/O, TYPE
DESCRIPTION
FPD-LINK INPUT INTERFACE
RxCLKIN-
35
I, LVDS
Inverting LVDS Clock Input
The pair requires external 100-Ω differential termination for standard LVDS levels
RxCLKIN+
36
I, LVDS
True LVDS Clock Input
The pair requires external 100-Ω differential termination for standard LVDS levels
RxIN[3:0]- 37, 33, 31, 29
I, LVDS
Inverting LVDS Data Inputs
Each pair requires external 100-Ω differential termination for standard LVDS levels
RxIN[3:0]+ 38, 34, 32, 30
I, LVDS
True LVDS Data Inputs
Each pair requires external 100-Ω differential termination for standard LVDS levels
LVCMOS PARALLEL INTERFACE
BKWD
22
I, LVCMOS Backward Compatible Mode Select
w/ pull down BKWD = 0, interfacing to DS90UH926/8Q-Q1 (Default)
BKWD = 1, interfacing to DS90UR906/8Q-Q1, DS90UR916Q
Requires a 10-kΩ pullup if set HIGH
GPIO[1:0]
40, 39
I/O, LVCMOS General Purpose I/O
w/ pull down See Table 1
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