DS90UH927Q-Q1 Datasheet, PDF (42/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
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Register Maps (continued)
ADD
(dec)
101
102
ADD
(hex)
0x65
0x66
Table 5. Serial Control Bus Registers (continued)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
Pattern
7
0x00
Reserved
Generator
Configuration
6
RW
Checkerboa Scale Checkered Patterns:
rd Scale 0: Normal operation (each square is 1x1 pixel)
(default)
1: Scale checkered patterns (VCOM and
checkerboard) by 8 (each square is 8x8 pixels)
Setting this bit gives better visibility of the checkered
patterns.
5
RW
Custom
Use Custom Checkerboard Color
Checkerboa 0: Use white and black in the Checkerboard pattern
rd
(default)
1: Use the Custom Color and black in the
Checkerboard pattern
4
RW
PG 18–bit
Mode
18-bit Mode Select:
0: Enable 24-bit pattern generation. Scaled patterns
use 256 levels of brightness. (default)
1: Enable 18-bit color pattern generation. Scaled
patterns will have 64 levels of brightness and the R,
G, and B outputs use the six most significant color
bits.
3
RW
External
Clock
Select External Clock Source:
0: Selects the internal divided clock when using
internal timing (default)
1: Selects the external pixel clock when using internal
timing. This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
2
RW
Timing
Select
Timing Select Control:
0: the Pattern Generator uses external video timing
from the pixel clock, Data Enable, Horizontal Sync,
and Vertical Sync signals. (default)
1: The Pattern Generator creates its own video timing
as configured in the Pattern Generator Total Frame
Size, Active Frame Size. Horizontal Sync Width,
Vertical Sync Width, Horizontal Back Porch, Vertical
Back Porch, and Sync Configuration registers.
See TI App Note AN-2198 Exploring the Internal Test
Pattern Generation Feature of 720p (SNLA132).
1
RW
Color Invert
Enable Inverted Color Patterns:
0: Do not invert the color output. (default)
1: Invert the color output.
See TI App Note AN-2198 Exploring the Internal Test
Pattern Generation Feature of 720p (SNLA132).
0
RW
Auto Scroll
Auto Scroll Enable:
0: The Pattern Generator retains the current pattern.
(default)
1: The Pattern Generator will automatically move to
the next enabled pattern after the number of frames
specified in the Pattern Generator Frame Time
(PGFT) register.
See TI App Note AN-2198 Exploring the Internal Test
Pattern Generation Feature of 720p (SNLA132).
PGIA
7:0
RW
0x00 PG Indirect This 8-bit field sets the indirect address for accesses
Address
to indirectly-mapped registers. It should be written
prior to reading or writing the Pattern Generator
Indirect Data register.
See TI App Note AN-2198 Exploring the Internal Test
Pattern Generation Feature of 720p (SNLA132)
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