DS90UH927Q-Q1 Datasheet, PDF (34/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
www.ti.com
Register Maps (continued)
ADD
(dec)
6
7
8
10
11
12
Table 5. Serial Control Bus Registers (continued)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
0x06 DES ID
7:1
RW
0x00 DES Device 7-bit Deserializer Device ID
ID
Configures the I²C Slave ID of the remote
Deserializer. A value of 0 in this field disables I²C
access to the remote Deserializer. This field is
automatically configured by the Bidirectional Control
Channel once RX Lock has been detected. Software
may overwrite this value, but should also assert the
FREEZE DEVICE ID bit to prevent overwriting by the
Bidirectional Control Channel.
0
Reserved
0x07 Slave ID 0
7:1
RW
0X00 Slave
7-bit Remote Slave Device ID 0
Device ID 0 Configures the physical I²C address of the remote I²C
Slave device attached to the remote Deserializer. If an
I²C transaction is addressed to the Slave Device Alias
ID 0, the transaction will be remapped to this address
before passing the transaction across the Bidirectional
Control Channel to the Deserializer.
0
Reserved
0x08 Slave Alias 0
7:1
RW
0x00 Slave
7-bit Remote Slave Device Alias ID 0 Configures the
Device
decoder for detecting transactions designated for an
Alias ID 0 I²C Slave device attached to the remote Deserializer.
The transaction will be remapped to the address
specified in the Slave ID 0 register. A value of 0 in this
field disables access to the remote I²C Slave.
0
Reserved
0x0A CRC Errors
7:0
R
0x00 CRC Error Number of Back Channel CRC errors – 8 least
LSB
significant bits. Cleared by 0x04[5]
0x0B
7:0
R
0x00 CRC Error Number of Back Channel CRC errors – 8 most
MSB
significant bits. Cleared by 0x04[5]
0x0C General Status 7:4
0x00
Reserved
3
R
BIST CRC
Error
Back Channel CRC error during BIST communication
with Deserializer. This bit is cleared upon loss of link,
restart of BIST, or assertion of CRC ERROR RESET
in register 0x04.
0: No CRC errors detected during BIST (default)
1: CRC Errors detected during BIST
2
R
PCLK
Detect
Pixel Clock Status
0: Valid PCLK not detected (default)
1: Valid PCLK detected
1
R
DES Error
CRC error during BIST communication with
Deserializer. This bit is cleared upon loss of link or
assertion of 0x04[5]
0: No CRC errors detected (default)
1: CRC errors detected
0
R
LINK Detect LINK Detect Status
0: Cable link not detected (default)
1: Cable link detected
34
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