DS90UH927Q-Q1 Datasheet, PDF (40/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
www.ti.com
Register Maps (continued)
ADD
(dec)
28
29
30
32
ADD
(hex)
0x1C
0x1D
0x1F
0x20
Table 5. Serial Control Bus Registers (continued)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
GPIO Pin
Status 1
7
R
0x00 GPIO_REG GPIO_REG7 Input Pin Status
7 Pin Status Status valid only if set to GPI (input) mode
6
R
GPIO_REG GPIO_REG6 Input Pin Status
6 Pin Status Status valid only if set to GPI (input) mode
5
R
GPIO_REG GPIO_REG5 Input Pin Status
5 Pin Status Status valid only if set to GPI (input) mode
4
Reserved
3
R
GPIO3 Pin GPIO3 Input Pin Status
Status
Status valid only if set to GPI (input) mode
2
R
GPIO2 Pin GPIO2 Input Pin Status
Status
Status valid only if set to GPI (input) mode
1
R
GPIO1 Pin GPIO1 Input Pin Status
Status
Status valid only if set to GPI (input) mode
0
R
GPIO0 Pin GPIO0 Input Pin Status
Status
Status valid only if set to GPI (input) mode
GPIO Pin
Status 2
7:1
0x00
Reserved
0
R
GPIO_REG GPIO_REG8 Input Pin Status
8 Pin Status Status valid only if set to GPI (input) mode
Frequency
Counter
7:0
RW
0x00 Frequency Frequency Counter Control
Counter
Write: Measure number of pixel clock periods in
written interval (40ns units)
Read: Return number of pixel clock periods counted
Deserializer
Capabilities
7
RW
0x00 Freeze DES Freeze Deserializer Capabilities
CAP
Prevent auto-loading of the Deserializer Capabilities
by the Bidirectional Control Channel. The Capabilities
will be frozen at the values written in registers 0x20
and 0x21.
0: Normal operation (default)
1: Freeze
6:2
Reserved
1
RW
HD Audio
Deserializer supports 24-bit video concurrently with
HD audio
This field is automatically configured by the
Bidirectional Control Channel once RX Lock has been
detected. Software may overwrite this value, but must
also set the FREEZE DES CAP bit to prevent
overwriting by the Bidirectional Control Channel.
0: Normal operation (default)
1: Freeze
0
RW
FC GPIO
Deserializer supports GPIO in the Forward Channel
Frame
This field is automatically configured by the
Bidirectional Control Channel once RX Lock has been
detected. Software may overwrite this value, but must
also set the FREEZE DES CAP bit to prevent
overwriting by the Bidirectional Control Channel.
0: Normal operation (default)
1: Freeze
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