DS90UH927Q-Q1 Datasheet, PDF (17/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

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DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Feature Description (continued)
7.3.6.1 BIST Configuration and Status
The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may
select either an external PCLK or the 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK,
the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration
register.
When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back
Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received
containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel
frame.
The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a
half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS
output until reset (new BIST or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on
PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST.
See Figure 14 for the BIST mode flow diagram.
Sample BIST Sequence
Step 1: For the DS90UH927Q-Q1 paired with a FPD-Link III Deserializer, BIST Mode is enabled via the BISTEN
pin of Deserializer. The desired clock source is selected through the deserializer BISTC pin.
Step 2: The DS90UH927Q-Q1 serializer is awakened through the back channel if it is not already on. An all-
zeros pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to the deserializer.
Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of
the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is
detected, the PASS pin will switch low for one half of the clock period. During the BIST, the PASS output can be
monitored and counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will remain HIGH. If
there one or more errors were detected, the PASS output will output constant LOW. The PASS output state is
held until a new BIST is run, the device is RESET, or the device is powered down. BIST duration is user-
controlled and may be of any length.
The link returns to normal operation after the deserializer BISTEN pin is low. Figure 15 shows the waveform
diagram of a typical BIST for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most
cases it is difficult to generate errors due to the robustness of the link (differential data transmission, and so
forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or
reducing signal condition enhancements (Rx Equalization).
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