DS90UH927Q-Q1 Datasheet, PDF (1/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

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DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
DS90UH927Q-Q1 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP
1 Features
•1 Integrated HDCP Cipher Engine with On-Chip Key
Storage
• Bidirectional Control Channel Interface with I²C
Compatible Serial Control Bus
• Low EMI FPD-Link Video Input
• Supports High Definition (720p) Digital Video
Format
• 5-MHz to 85-MHz PCLK Supported
• RGB888 + VS, HS, DE and I²S Audio Supported
• Up to 4 I²S Digital Audio Inputs for Surround
Sound Applications
• 4 Bidirectional GPIO Channels with 2 Dedicated
Pins
• Single 3.3-V Supply with 1.8-V or 3.3-V
Compatible LVCMOS I/O Interface
• AC-Coupled STP Interconnect up to 10 Meters
• DC-Balanced & Scrambled Data with Embedded
Clock
• Supports HDCP Repeater Application
• Internal Pattern Generation
• Low Power Modes Minimize Power Dissipation
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified
• > 8-kV HBM and ISO 10605 ESD Rating
• Backward Compatible Modes
2 Applications
• Automotive Displays for Navigation
• Rear Seat Entertainment Systems
3 Description
The DS90UH927Q-Q1 serializer, in conjunction with
a DS90UH928Q-Q1 or DS90UH926Q-Q1
deserializer, provides a solution for secure distribution
of content-protected digital video within automotive
entertainment systems. This chipset translates a
FPD-Link video interface into a single-pair high-speed
serialized interface. The digital video data is protected
using the industry standard High-Bandwidth Digital
Content Protection (HDCP) copy protection scheme.
The FPD-Link III serial bus scheme supports full
duplex, high speed forward channel data
transmission and low-speed back channel
communication over a single differential link.
Consolidation of audio, video, and control data over a
single differential pair reduces the interconnect size
and weight, while also eliminating skew issues and
simplifying system design.
The DS90UH927Q-Q1 serializer embeds the clock,
content protects the data payload, and level shifts the
signals to high-speed differential signaling. Up to 24
RGB data bits are serialized along with three video
control signals, and up to four I²S data inputs.
The FPD-Link data interface allows for easy
interfacing with data sources while also minimizing
EMI and bus width. EMI on the high-speed FPD-Link
III bus is minimized using low voltage differential
signaling, data scrambling and randomization, and
dc-balancing.
The HDCP cipher engine is implemented in both the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
Device Information⁽¹⁾
PART NUMBER PACKAGE
BODY SIZE (NOM)
DS90UH927Q-Q1 WQFN (40)
6.00 mm x 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
FPD-Link
Application Diagram
FPD-Link
VDDIO
VDD33
(1.8V or 3.3V) (3.3V)
VDD33
VDDIO
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RxIN3+/-
RxIN2+/-
RxIN1+/-
RxIN0+/-
RxCLKIN+/-
PDB
INTB
I2S
6
SCL
SDA
IDx
DOUT+
DOUT-
DS90UH927Q-Q1
Serializer
FPD-Link III
1 Pair/AC Coupled
1003 STP Cable
MAPSEL
LFMODE
REPEAT
BKWD
OEN
OSS_SEL
PDB
MAPSEL
LFMODE
BISTEN
MODE_SEL
RIN+
RIN-
DS90UH928Q-Q1
Deserializer
TxOUT3+/-
TxOUT2+/-
TxOUT1+/-
TxOUT0+/-
TxCLKOUT+/-
INTB_IN
LOCK
6
PASS
I2S
MCLK
SCL
SDA
IDx
RGB Display
720p
24-bit Color Depth
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.