DS90UH927Q-Q1 Datasheet, PDF (51/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

www.ti.com
DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Register Maps (continued)
ADD
(dec)
208
209
210
211
240
241
242
243
244
245
Table 5. Serial Control Bus Registers (continued)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
0xD0 IND STS
7
RW
0x00 IA Reset Indirect Access Reset
Setting this bit to a 1 will reset the I²C Master in the
HDCP Receiver. As this may leave the I²C bus in an
indeterminate state, it should only be done if the
Indirect Access mechanism is not able to complete
due to an error on the destination I²C bus.
6
5
RW
4
RW
I2C TO DIS
I2C Fast
Reserved
I²C Timeout Disable
Setting this bit to a 1 will disable the bus timeout
function in the I²C master. When enabled, the bus
timeout function allows the I²C master to assume the
bus is free if no signaling occurs for more than 1
second.
I²C Fast mode Enable
Setting this bit to a 1 will enable the I²C Master in the
HDCP Receiver to operation with Fast mode timing. If
set to a 0 (default), the I²C Master will operate with
Standard mode timing.
3:2
Reserved
1
R
IA ACK
Indirect Access Acknowledge
The acknowledge bit indicates that a valid
acknowledge was received upon completion of the I²C
read or write to the slave. A value of 0 (default)
indicates the read/write did not complete successfully.
0
R
IA DONE
Indirect Access Done
Set to a 1 to indicate completion of Indirect Register
Access. This bit will be cleared or read or by start of a
new Indirect Register Access.
0xD1 IND SAR
7:1
RW
0x00 IA SADDR Indirect Access Slave Address
This field should be programmed with the slave
address for the I²C slave to be accessed.
0
RW
IA RW
Indirect Access Read/Write
0: Write (default)
1: Read
0xD2 IND OAR
7:0
RW
0x00 IA Offset Indirect Access Offset
It is programmed with the register address for the I²C
indirect access.
0xD3 IND DATA
7:0
RW
0x00 IA Data
Indirect Access Data
For an indirect write, It is written with the write data.
For an indirect read, it contains the result of a
successful read.
0xF0 HDCP TX ID
7:0
R
0x5F ID0
First byte ID code, ‘_’
0xF1
7:0
R
0x55 ID1
Second byte of ID code, ‘U’
0xF2
7:0
R
0x48 ID2
Third byte of ID code. ‘H'
0xF3
7:0
R
0x39 ID3
Forth byte of ID code: ‘9’
0xF4
7:0
R
0x32 ID4
Fifth byte of ID code: “2”
0xF5
7:0
R
0x37 ID5
Sixth byte of ID code: “7”
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UH927Q-Q1
Submit Documentation Feedback
51