DS90UH927Q-Q1 Datasheet, PDF (30/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Device Functional Modes (continued)
L3 < 60 mm
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TX
(UH927)
RX
(UH928)
R1=100
R2=100
L1 < 75 mm
L2 < 60 mm
TX
(UH927)
L3 < 60 mm
TX
(UH927)
Figure 24. FPD-Link Fan-Out Electrical Requirements
7.5 Programming
7.5.1 Serial Control Bus
The DS90UH927Q-Q1 may also be configured by the use of an I²C compatible serial control bus. Multiple
devices may share the serial control bus (up to 10 device addresses supported). The device address is set via a
resistor divider (R1 and R2 — see Figure 25) connected to the IDx pin.
VDD33
HOST
SCL
SDA
VDD33
R1
VR2
IDx
4.7k
4.7k
R2
SER
SCL
SDA
To other
Devices
Figure 25. Serial Control Bus Connection
The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial
Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to V_DD33 or V_DDIO =
3.0 V to 3.6 V. For most applications, a 4.7-kΩ pullup resistor to V_DD33 is recommended. However, the pullup
resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled
High, or driven Low.
The IDx pin configures the control interface to one of 10 possible device addresses. A pullup resistor and a
pulldown resistor may be used to set the appropriate voltage ratio between the IDx input pin (V_R2) and V_DD33,
each ratio corresponding to a specific device address. See Table 5.
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