DS90UH927Q-Q1 Datasheet, PDF (33/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

www.ti.com
DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Register Maps (continued)
ADD
(dec)
4
5
Table 5. Serial Control Bus Registers (continued)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
0x04 Mode Select
7
RW
0x80 Failsafe
Input Failsafe State
State
0: Failsafe to High
1: Failsafe to Low (default)
6
Reserved
5
RW
CRC Error
Reset
Clear back channel CRC Error Counters
This bit is NOT self-clearing
0: Normal Operation (default)
1: Clear Counters
4
Reserved
3
RW
BKWD
ModeOverri
de
Backward Compatible mode set by BKWD pin or
register
0: BC mode is set by BKWD pin (default)
1: BC mode is set by register bit
2
RW
BKWD
Backward compatibility mode, device to pair with
DS90UR906Q, DS90UR908Q, or DS90UR916Q
0: Normal HDCP device (default)
1: Compatible with 906/908/916
1
RW
LFMODE
Override
Frequency mode set by LFMODE pin or register
0: Frequency mode is set by LFMODE pin (default)
1: Frequency mode is set by register bit
0x05 I²C Control
0
RW
LFMODE
Frequency mode select
0: High frequency mode (15 MHz ≤ RxCLKIN ≤ 85
MHz) (default)
1: Low frequency mode (5 MHz ≤ RxCLKIN < 15
MHz)
7:5
0x00
Reserved
4:3
RW
SDA Output
Delay
SDA output delay
Configures output delay on the SDA output. Setting
this value will increase output delay in units of 40 ns.
Nominal output delay values for SCL to SDA are:
00: 240 ns (default)
01: 280 ns
10: 320 ns
11: 360 ns
2
RW
1
RW
0
RW
Local Write
Disable
I²C Bus
Timer
Speedup
I²C Bus
timer
Disable
Disable Remote Writes to Local Registers
Setting this bit to a 1 will prevent remote writes to
local device registers from across the control channel.
This prevents writes to the Serializer registers from an
I²C master attached to the Deserializer. Setting this
bit does not affect remote access to I²C slaves at the
Serializer.
0: Enable (default)
1: Disable
Speed up I²C Bus Watchdog Timer
0: Watchdog Timer expires after ~1 s (default)
1: Watchdog Timer expires after ~50 µs
Disable I²C Bus Watchdog Timer
When the I²C Watchdog Timer may be used to detect
when the I²C bus is free or hung up following an
invalid termination of a transaction. If SDA is high and
no signaling occurs for approximately 1s, the I²C bus
will be assumed to be free. If SDA is low and no
signaling occurs, the device will attempt to clear the
bus by driving 9 clocks on SCL
0: Enable (default)
1: Disable
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UH927Q-Q1
Submit Documentation Feedback
33