DS90UH927Q-Q1 Datasheet, PDF (31/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

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DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
Programming (continued)
Table 4. Serial Control Bus Addresses for IDx
#
Ideal Ratio
V_R2 / V_DD33
1
0
2
0.306
3
0.350
4
0.393
5
0.440
6
0.483
7
0.529
8
0.572
9
0.618
10
0.768
Ideal V_R2
(V)
0
1.011
1.154
1.298
1.452
1.594
1.745
1.887
2.040
2.535
Suggested Resistor Suggested Resistor
R1 kΩ (1% tol)
R2 kΩ (1% tol)
Open
40.2 or >10
221
97.6
210
113
196
127
182
143
169
158
147
165
143
191
121
196
90.9
301
Address 7'b
0x0C
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
Address 8'b
0x18
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x32
0x34
0x36
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See
Figure 26.
SDA
SCL
S
START condition, or
START repeat condition
Figure 26. START and STOP Conditions
P
STOP condition
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 27 and a WRITE is shown in Figure 28.
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
S
Slave Address
a
AA
21
A
0
1
c
k
Data
a
c
k
P
Figure 27. Serial Control Bus — READ
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
Data
a
c
k
P
Figure 28. Serial Control Bus — WRITE
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