DS90UH927Q-Q1 Datasheet, PDF (46/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
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Register Maps (continued)
ADD
(dec)
162
163
192
Table 5. Serial Control Bus Registers (continued)
ADD
(hex)
Register Name
Bit
Register
Type
Default
(hex)
Function
Description
0xA2 RX BSTATUS1 7:4
0x00
Reserved
3
R
Max
Cascade
Maximum Cascade Exceeded: Indicates a topology
error was detected — more than seven levels of
repeaters have been cascaded together.
2:0
R
Cascade
Depth
Indicates the number of attached levels of devices for
the Repeater.
0xA3 KSV FIFO
7:0
R
0x00 KSV FIFO KSV FIFO
Each read of the KSV FIFO returns one byte of the
KSV FIFO list composed by the downstream
Receiver.
0xC0 HDCP DBG
7:4
0x00
Reserved
3
RW
RGB
CHKSUM
Enable RGB video line checksum
Enables sending of ones-complement checksum for
each 8-bit RGB data channel following end of each
video data line.
2
RW
Fast LV
Fast Link Verification
HDCP periodically verifies that the HDCP Receiver is
correctly synchronized. Setting this bit will increase
the rate at which synchronization is verified. When set
to a 1, Pj is computed every 2 frames and Ri is
computed every 16 frames. When set to a 0, Pj is
computed every 16 frames and Ri is computed every
128 frames.
1
RW
0
RW
TMR Speed
Up
HDCP I2C
Fast
Timer Speedup
Speed up HDCP authentication timers.
HDCP I²C Fast Mode Enable
Setting this bit to a 1 will enable the HDCP I²C Master
in the HDCP Receiver to operate with Fast mode
timing. If set to a 0, the I²C Master will operate with
Standard mode timing. This bit is mirrored in the
IND_STS register.
46
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