DS90UH927Q-Q1 Datasheet, PDF (32/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
www.ti.com
The I²C Master located at the DS90UH927Q-Q1 serializer must support I²C clock stretching. For more
information on I²C interface requirements and throughput considerations, please refer to I2C Communication
Over FPD-Link III with Bidirectional Control Channel (SNLA131).
7.6 Register Maps
ADD
(dec)
0
ADD
(hex)
0x00
Register Name
I²C Device ID
1
0x01 Reset
3
0x03 General
Configuration
Table 5. Serial Control Bus Registers
Bit
Register
Type
Default
(hex)
Function
Description
7:1
RW
0
RW
IDx Device ID 7–bit address of Serializer
Note: Read-only unless bit 0 is set
ID Setting
I²C ID Setting
0: Device ID is from IDx pin
1: Register I²C Device ID overrides IDx pin
7
RW
0x00 Remote
Remote Auto Power Down
Auto Power 0: Do not power down when no Bidirectional Control
Down
Channel link is detected (default)
1: Enable power down when no Bidirectional Control
Channel link is detected
6:2
Reserved.
1
RW
Digital
RESET1
Reset the entire digital block including registers
This bit is self-clearing.
0: Normal operation (default)
1: Reset
0
RW
Digital
RESET0
Reset the entire digital block except registers
This bit is self-clearing
0: Normal operation (default)
1: Reset
7
RW
0xD2 Back
Back Channel Check Enable
channel
0: Disable
CRC
1: Enable (default)
Checker
Enable
6
5
RW
I²C Remote
Write Auto
Acknowledg
e
Reserved.
Automatically Acknowledge I²C Remote Write When
enabled, I²C writes to the Deserializer (or any remote
I²C Slave, if I²C PASS ALL is enabled) are
immediately acknowledged without waiting for the
Deserializer to acknowledge the write. This allows
higher throughput on the I²C bus. Note: this mode will
prevent any NACK or read/write error indication from
a remote device from reaching the I²C master.
0: Disable (default)
1: Enable
4
RW
3
RW
Filter
Enable
I²C Pass-
through
HS, VS, DE two clock filter When enabled, pulses
less than two full PCLK cycles on the DE, HS, and VS
inputs will be rejected
0: Filtering disable
1: Filtering enable (default)
I²C Pass-Through Mode
Read/Write transactions matching any entry in the
DeviceAlias registers will be passed through to the
remote deserializer I²C interface.
0: Pass-Through Disabled (default)
1: Pass-Through Enabled
2
Reserved
1
RW
PCLK Auto Switch over to internal OSC in the absence of PCLK
0: Disable auto-switch
1: Enable auto-switch (default)
0
RW
TRFB
Reserved
32
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