DS90UH927Q-Q1 Datasheet, PDF (15/68 Pages) Texas Instruments – 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP

www.ti.com
7 Detailed Description
DS90UH927Q-Q1
SNLS433C – NOVEMBER 2012 – REVISED JANUARY 2015
7.1 Overview
The DS90UH927Q-Q1 converts a FPD-Link interface (4 LVDS data channels + 1 LVDS Clock) to a FPD-Link III
interface. This device transmits a 35-bit symbol over a single serial pair operating at up to a 2.975-Gbps line rate.
The serial stream contains an embedded clock, video control signals, RGB video data, and audio data. The
payload is DC-balanced to enhance signal quality and support AC coupling.
The DS90UH927Q-Q1 applies encryption to the video data using a High-Bandwidth Digital Content Protection
(HDCP) Cipher, and transmits the encrypted data out through the FPD-Link III interface. Audio encryption is
supported. On chip non-volatile memory stores the HDCP keys. All key exchanges are conducted over the FPD-
Link III bidirectional control interface.
The DS90UH927Q-Q1 serializer is intended for use with a DS90UH928Q-Q1 or DS90UH926Q-Q1 deserializer,
but is also backward compatible with DS90UR906Q, DS90UR908Q, DS90UR910Q, and DS90UR916Q FPD-Link
II deserializers.
The DS90UH927Q-Q1 serializer and DS90UH928Q-Q1 or DS90UH926Q-Q1 deserializer incorporate an I²C
compatible interface. The I²C compatible interface allows programming of serializer or deserializer devices from a
local host controller. In addition, the devices incorporate a bidirectional control channel (BCC) that allows
communication between serializer/deserializer as well as remote I²C slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward
channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to
serializer). Through this interface, the BCC provides a mechanism to bridge I²C transactions across the serial link
from one I²C bus to another. The implementation allows for arbitration with other I²C compatible masters at either
side of the serial link.
7.2 Functional Block Diagram
RxIN3+/-
RxIN2+/-
RxIN1+/-
RxIN0+/-
RxCLKIN+/-
8
I2S / GPIO
LFMODE
MAPSEL
BKWD
REPEAT
PDB
INTB
SDA
SCL
IDx
REGULATOR
PLL
Timing and
Control
CMF
DOUT+
DOUT-
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DS90UH927Q-Q1
Submit Documentation Feedback
15