SMJ320VC5416HFGW10 Datasheet, PDF (88/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.15.2 HPI16 Mode
Table 5--35 and Table 5--36 assume testing over recommended operating conditions and P = 1 / (2 * processor
clock) (see Figure 5--32 through Figure 5--34). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are
shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set,
Volume 5: Enhanced Peripherals (literature number SPRU302) for addition information.
Table 5--35. HPI16 Mode Timing Requirements
t_su(HBV-DSL)
t_h(DSL-HBV)
Setup time, HR/W valid before DS falling edge
Hold time, HR/W valid after DS falling edge
t_su(HAV-DSH)
t_su(HAV-DSL)
t_h(DSH-HAV)
t_w(DSL)
t_w(DSH)
Setup time, address valid before DS rising edge (write)
Setup time, address valid before DS falling edge (read)
Hold time, address valid after DS rising edge
Pulse duration, DS low
Pulse duration, DS high
Memory accesses with no DMA activity.
Reads
Writes
t_c(DSH-DSH)
Cycle time, DS rising edge to
Reads
next DS rising edge
Memory accesses with 16-bit DMA activity.
Writes
Reads
Memory accesses with 32-bit DMA activity.
Writes
t_su(HDV-DSH)W
t_h(DSH-HDV)W
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge, write
* Not production tested.
5416-100
MIN
MAX
6
5
5*
--(4P -- 6)*
1*
30*
10*
10P + 30*
10P + 10*
16P + 30*
16P + 10*
24P + 30*
24P + 10*
8
2
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
78 SGUS035A
April 2003 -- Revised July 2003