SMJ320VC5416HFGW10 Datasheet, PDF (11/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

1 SMJ320VC5416 Features
D Processed to MIL-PRF-38535 (QML)
D Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D 40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
D 17 x 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
D Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D Data Bus With a Bus Holder Feature
D Extended Addressing Mode for 8M x 16-Bit
Maximum Addressable External Program
Space
D 128K x 16-Bit On-Chip RAM Composed of:
-- Eight Blocks of 8K x 16-Bit On-Chip
Dual-Access Program/Data RAM
-- Eight Blocks of 8K x 16-Bit On-Chip
Single-Access Program RAM
D 16K x 16-Bit On-Chip ROM Configured for
Program Memory
D Enhanced External Parallel Interface (XIO2)
D Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
D Block-Memory-Move Instructions for Better
Program and Data Management
Features
D Instructions With a 32-Bit Long Word
Operand
D Instructions With Two- or Three-Operand
Reads
D Arithmetic Instructions With Parallel Store
and Parallel Load
D Conditional Store Instructions
D Fast Return From Interrupt
D On-Chip Peripherals
-- Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
-- On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With
External Clock Source
-- One 16-Bit Timer
-- Six-Channel Direct Memory Access
(DMA) Controller
-- Three Multichannel Buffered Serial Ports
(McBSPs)
-- 8/16-Bit Enhanced Parallel Host-Port
Interface (HPI8/16)
D Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D CLKOUT Off Control to Disable CLKOUT
D On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1^† (JTAG) Boundary Scan
Logic
D 164-Pin Ceramic Quad Flatpack (CQFP)
(HFG Suffix)
D 10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS)
D 3.3-V I/O Supply Voltage
D 1.5-V Core Supply Voltage
D --55°C to 115°C Operating Temperature
Range, QML Processing
† _{IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.}
April 2003 -- Revised July 2003
SGUS035A
1