SMJ320VC5416HFGW10 Datasheet, PDF(49/96 Page) Texas Instruments

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SMJ320VC5416HFGW10 Datasheet, PDF (49/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

◁

Functional Overview

3.17 DMA Subbank Addressed Registers

The direct memory access (DMA) controller has several control registers associated with it. The main control

the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single

memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular

with autoincrement (DMSDI) is used to access (read or write) the selected register.

When the DMSDI register is used to access the subbank, the subbank address is automatically

postincremented so that a subsequent access affects the next register within the subbank. This autoincrement

feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature

is not required, the DMSDN register should be used to access the subbank. Table 3--17 shows the DMA

controller subbank addressed registers and their corresponding subaddresses.

NAME

DMSRC0

DMDST0

DMCTR0

DMSFC0

DMMCR0

DMSRC1

DMDST1

DMCTR1

DMSFC1

DMMCR1

DMSRC2

DMDST2

DMCTR2

DMSFC2

DMMCR2

DMSRC3

DMDST3

DMCTR3

DMSFC3

DMMCR3

DMSRC4

DMDST4

DMCTR4

DMSFC4

DMMCR4

DMSRC5

DMDST5

DMCTR5

DMSFC5

DMMCR5

DMSRCP

ADDRESS

56h/57h

Table 3--17. DMA Subbank Addressed Registers

SUB-

ADDRESS

DESCRIPTION

00h

DMA channel 0 source address register

01h

DMA channel 0 destination address register

02h

DMA channel 0 element count register

03h

DMA channel 0 sync select and frame count register

04h

DMA channel 0 transfer mode control register

05h

DMA channel 1 source address register

06h

DMA channel 1 destination address register

07h

DMA channel 1 element count register

08h

DMA channel 1 sync select and frame count register

09h

DMA channel 1 transfer mode control register

0Ah

DMA channel 2 source address register

0Bh

DMA channel 2 destination address register

0Ch

DMA channel 2 element count register

0Dh

DMA channel 2 sync select and frame count register

0Eh

DMA channel 2 transfer mode control register

0Fh

DMA channel 3 source address register

10h

DMA channel 3 destination address register

11h

DMA channel 3 element count register

12h

DMA channel 3 sync select and frame count register

13h

DMA channel 3 transfer mode control register

14h

DMA channel 4 source address register

15h

DMA channel 4 destination address register

16h

DMA channel 4 element count register

17h

DMA channel 4 sync select and frame count register

18h

DMA channel 4 transfer mode control register

19h

DMA channel 5 source address register

1Ah

DMA channel 5 destination address register

1Bh

DMA channel 5 element count register

1Ch

DMA channel 5 sync select and frame count register

1Dh

DMA channel 5 transfer mode control register

1Eh

DMA source program page address (common channel)

April 2003 -- Revised July 2003

SGUS035A

▷