SMJ320VC5416HFGW10 Datasheet, PDF (57/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
Table 5--4 and Table 5--5 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 5--3).
Table 5--4. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements
5416-100
MIN MAX
t_c(CI)
Cycle time, X2/CLKIN
t_f(CI)
Fall time, X2/CLKIN
t_r(CI)
Rise time, X2/CLKIN
t_w(CIL) Pulse duration, X2/CLKIN low
t_w(CIH) Pulse duration, X2/CLKIN high
* Not production tested.
20
4*
4*
4*
4*
UNIT
ns
ns
ns
ns
ns
Table 5--5. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics
PARAMETER
t_c(CO)
Cycle time, CLKOUT
t_d(CIH-CO)
Delay time, X2/CLKIN high to CLKOUT high/low
t_f(CO)
Fall time, CLKOUT
t_r(CO)
Rise time, CLKOUT
t_w(COL)
Pulse duration, CLKOUT low
t_w(COH)
Pulse duration, CLKOUT high
* Not production tested.
† _{It is recommended that the PLL clocking option be used for maximum frequency operation.}
‡ _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞.}
5416-100
MIN TYP MAX
10^†
‡
4
7
11
2*
2*
H --3*
H H + 1*
H -- 2*
H H + 1*
UNIT
ns
ns
ns
ns
ns
ns
X2/CLKIN
t_c(CI)
t_w(CIH)
t_w(CIL)
t_r(CI)
t_f(CI)
CLKOUT
t_c(CO)
t_d(CIH-CO)
t_f(CO)
t_r(CO)
t_w(COH)
t_w(COL)
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5--3. External Divide-by-Two Clock Timing
April 2003 -- Revised July 2003
SGUS035A
47