SMJ320VC5416HFGW10 Datasheet, PDF (63/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.8.3 I/O Read
Table 5--11 and Table 5--12 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5t_c(CO) (see Figure 5--8).
Table 5--11. I/O Read Timing Requirements
t_a(A)M1
Access time, read data access from address valid, first read access^†
t_su(D)R
Setup time, read data valid before CLKOUT low
t_h(D)R
Hold time, read data valid after CLKOUT low
† _{Address R/W, PS, DS, and IS timings are included in timings referenced as address.}
5416-100
MIN MAX
4H -- 9
7
0
UNIT
ns
ns
ns
Table 5--12. I/O Read Switching Characteristics
PARAMETER
t_d(CLKL-A)
Delay time, CLKOUT low to address valid^†
t_d(CLKL-IOSL)
Delay time, CLKOUT low to IOSTRB low
t_d(CLKL-IOSH)
Delay time, CLKOUT low to IOSTRB high
* Not production tested.
† _{Address R/W, PS, DS, and IS timings are included in timings referenced as address.}
5416-100
MIN MAX
-- 1*
4
-- 1*
4
-- 1*
4
UNIT
ns
ns
ns
CLKOUT
A[22:0]^†
D[15:0]
t_d(CLKL-A)
t_d(CLKL-IOSL)
t_d(CLKL-IOSH)
t_a(A)M1
t_su(D)R
t_h(D)R
t_d(CLKL-A)
IOSTRB
R/W^†
IS^†
† _{Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.}
Figure 5--8. Parallel I/O Port Read (IOSTRB = 0)
April 2003 -- Revised July 2003
SGUS035A
53