SMJ320VC5416HFGW10 Datasheet, PDF (51/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

3.18 Interrupts
Functional Overview
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3--18.
NAME
RS, SINTR
NMI, SINT16
SINT17
SINT18
SINT19
SINT20
SINT21
SINT22
SINT23
SINT24
SINT25
SINT26
SINT27
SINT28
SINT29
SINT30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT, SINT3
RINT0, SINT4
XINT0, SINT5
RINT2, SINT6
XINT2, SINT7
INT3, SINT8
HINT, SINT9
RINT1, SINT10
XINT1, SINT11
DMAC4,SINT12
DMAC5,SINT13
Reserved
Table 3--18. Interrupt Locations and Priorities
LOCATION
DECIMAL
HEX
PRIORITY
FUNCTION
0
00
1
Reset (hardware and software reset)
4
04
2
Nonmaskable interrupt
8
08
—
Software interrupt #17
12
0C
—
Software interrupt #18
16
10
—
Software interrupt #19
20
14
—
Software interrupt #20
24
18
—
Software interrupt #21
28
1C
—
Software interrupt #22
32
20
—
Software interrupt #23
36
24
—
Software interrupt #24
40
28
—
Software interrupt #25
44
2C
—
Software interrupt #26
48
30
—
Software interrupt #27
52
34
—
Software interrupt #28
56
38
—
Software interrupt #29
60
3C
—
Software interrupt #30
64
40
3
External user interrupt #0
68
44
4
External user interrupt #1
72
48
5
External user interrupt #2
76
4C
6
Timer interrupt
80
50
7
McBSP #0 receive interrupt (default)
84
54
8
McBSP #0 transmit interrupt (default)
88
58
9
McBSP #2 receive interrupt (default)
92
5C
10
McBSP #2 transmit interrupt (default)
96
60
11
External user interrupt #3
100
64
12
HPI interrupt
104
68
13
McBSP #1 receive interrupt (default)
108
6C
14
McBSP #1 transmit interrupt (default)
112
70
15
DMA channel 4 (default)
116
74
16
DMA channel 5 (default)
120--127
78--7F
—
Reserved
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 3--22.
15--14 13
12
11
10
9
Resvd DMAC5 DMAC4 XINT1 RINT1 HINT
8
7
6
5
4
3
INT3 XINT2 RINT2 XINT0 RINT0 TINT
2
INT2
1
INT1
0
INT0
Figure 3--22. IFR and IMR
April 2003 -- Revised July 2003
SGUS035A
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