SMJ320VC5416HFGW10 Datasheet, PDF (55/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.4 Package Thermal Resistance Characteristics
Table 5--1 provides the estimated thermal resistance characteristics for the recommended package types
used on the SMJ320VC5416 DSP.
Table 5--1. Thermal Resistance Characteristics
PARAMETER
R_ΘJC
HFG PACKAGE
1.82
UNIT
°C/W
5.5 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
a
access time
c
cycle time (period)
d
delay time
dis
disable time
en
enable time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
X
Unknown, changing, or don’t care level
Letters and symbols and their meanings:
H
High
L
Low
V
Valid
Z
High impedance
5.6 Internal Oscillator With External Crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent;
see Section 3.10) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock
frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The multiply ratio is determined by
the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30 Ω maximum and power dissipation of 1 mW. The connection of the required circuit, consisting
of the crystal and two load capacitors, is shown in Figure 5--2. The load capacitors, C₁ and C₂, should be
chosen such that the equation below is satisfied. C_L (recommended value of 10 pF) in the equation is the load
specified for the crystal.
C_L
=
C₁C₂
(C₁ + C₂)
Table 5--2. Input Clock Frequency Characteristics
f_x
Input clock frequency
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞.}
‡ _{It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.}
MIN MAX UNIT
10^† 20^‡
MHz
April 2003 -- Revised July 2003
SGUS035A
45