SMJ320VC5416HFGW10 Datasheet, PDF (64/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.8.4 I/O Write
Table 5--13 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t_c(CO) (see
Figure 5--9).
Table 5--13. I/O Write Switching Characteristics
PARAMETER
t_d(CLKL-A)
t_su(A)IOSL
Delay time, CLKOUT low to address valid^†
Setup time, address valid before IOSTRB low^†
t_d(CLKL-D)W
Delay time, CLKOUT low to write data valid
t_su(D)IOSH
t_h(D)IOSH
Setup time, data valid before IOSTRB high
Hold time, data valid after IOSTRB high
t_d(CLKL-IOSL)
Delay time, CLKOUT low to IOSTRB low
t_w(SL)IOS
Pulse duration, IOSTRB low
t_d(CLKL-IOSH)
Delay time, CLKOUT low to IOSTRB high
* Not production tested.
† _{Address R/W, PS, DS, and IS timings are included in timings referenced as address.}
5416-100
MIN MAX
-- 1*
4
2H -- 3
-- 1*
4
2H -- 5 2H + 6*
2H -- 5* 2H + 6*
-- 1*
4
2H -- 2*
-- 1*
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
A[22:0]^†
D[15:0]
t_d(CLKL-A)
t_su(A)IOSL
t_d(CLKL-D)W
t_d(CLKL-A)
t_d(CLKL-D)W
t_d(CLKL-IOSL)
t_su(D)IOSH
t_d(CLKL-IOSH)
t_h(D)IOSH
† _{Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.}
Figure 5--9. Parallel I/O Port Write (IOSTRB = 0)
54 SGUS035A
April 2003 -- Revised July 2003