SMJ320VC5416HFGW10 Datasheet, PDF (28/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
Table 3--5. Bank-Switching Control Register (BSCR) Fields
BIT
15
13--14
12
11--3
2
1
0
NAME
CONSEC^†
DIVFCT
IACKOFF
Rsvd
HBH
BH
Rsvd
RESET
VALUE
FUNCTION
Consecutive bank-switching. Specifies the bank-switching mode.
1
CONSEC = 0:
Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for
continuous memory reads (i.e., no starting and trailing cycles between read cycles).
Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:
CONSEC = 1: _{starting cycle, read cycle, and trailing cycle.}
CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency
equal to 1/(DIVFCT+1) of the DSP clock.
DIVFCT = 00: CLKOUT is not divided.
11 _{DIVFCT = 01: CLKOUT is divided by 2 from the DSP clock.}
DIVFCT = 10: CLKOUT is divided by 3 from the DSP clock.
DIVFCT = 11: CLKOUT is divided by 4 from the DSP clock (default value following reset).
IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.
1 IACKOFF = 0: The IACK signal output off function is disabled.
IACKOFF = 1: The IACK signal output off function is enabled.
-- Reserved
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.
HBH = 0:
0
HBH = 1:
The bus holder is disabled except when HPI16 = 1.
The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous
logic level.
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.
BH = 0:
0
BH = 1:
The bus holder is disabled.
The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic
level.
-- Reserved
† _{For additional information, see Section 3.11 of this document.}
The 5416 has an internal register that holds the MSB of the last address used for a read or write operation
in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address
used for the current read does not match that contained in this internal register, the MSTRB (memory strobe)
signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new
address. The contents of the internal register are replaced with the MSB for the read of the current address.
If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs.
In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory
bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts
are avoided by inserting an extra cycle. For more information, see Section 3.11 of this document.
The bank-switching mechanism automatically inserts one extra cycle in the following cases:
• A memory read followed by another memory read from a different memory bank.
• A program-memory read followed by a data-memory read.
• A data-memory read followed by a program-memory read.
• A program-memory read followed by another program-memory read from a different page.
18 SGUS035A
April 2003 -- Revised July 2003