SMJ320VC5416HFGW10 Datasheet, PDF (16/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Introduction
Table 2--2. Signal Descriptions (Continued)
TERMINAL
NAME
I/O^†
DESCRIPTION
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15--A0. IACK also goes into the high-impedance state when OFF is low.
INT0^‡
INT1^‡
INT2^‡
INT3^‡
External user interrupt inputs. INT0--INT3 are maskable and are prioritized by the interrupt mask register (IMR)
I
and the interrupt mode bit. INT0 --INT3 can be polled and reset by way of the interrupt flag register (IFR).
NMI^‡
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program counter to
RS^‡
I
0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects
various registers and status bits.
MP/MC
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the
internal program ROM is mapped into the upper 16K words of program memory space. If the pin is driven high
I
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode
that is selected at reset.
MULTIPROCESSING SIGNALS
BIO^‡
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
I
conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
instruction, and all other instructions sample BIO during the read phase of the pipeline.
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
XF
O/Z
by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low,
and is set high at reset.
MEMORY CONTROL SIGNALS
DS
PS
IS
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
O/Z
communicating to a particular external space. Active period corresponds to valid address information. DS, PS,
and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance
state when OFF is low.
MSTRB
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
O/Z data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when OFF is low.
READY
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
I
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
R/W
O/Z in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the
high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.
IOSTRB
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
O/Z device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
HOLD
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the 5416, these lines go into the high-impedance state.
† _{I = Input, O = Output, Z = High-impedance, S = Supply}
‡ _{These pins have Schmitt trigger inputs.}
§ _{This pin has an internal bus holder controlled by way of the BSCR register.}
¶ _{This pin has an internal pullup resistor.}
# _{This pin has an internal pulldown resistor.}
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SGUS035A
April 2003 -- Revised July 2003