SMJ320VC5416HFGW10 Datasheet, PDF (48/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.16 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register within
the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register.
Table 3--16 shows the McBSP control registers and their corresponding subaddresses.
McBSP0
NAME ADDRESS
SPCR10
39h
SPCR20
39h
RCR10
39h
RCR20
39h
XCR10
39h
XCR20
39h
SRGR10
39h
SRGR20
39h
MCR10
39h
MCR20
39h
RCERA0
39h
RCERB0
39h
XCERA0
39h
XCERB0
39h
PCR0
39h
RCERC0
39h
RCERD0
39h
XCERC0
39h
XCERD0
39h
RCERE0
39h
RCERF0
39h
XCERE0
39h
XCERF0
39h
RCERG0
39h
RCERH0
39h
XCERG0
39h
XCERH0
39h
Table 3--16. McBSP Control Registers and Subaddresses
McBSP1
NAME ADDRESS
McBSP2
SUB-
NAME ADDRESS ^ADDRESS
DESCRIPTION
SPCR11
49h
SPCR12
35h
00h
Serial port control register 1
SPCR21
49h
SPCR22
35h
01h
Serial port control register 2
RCR11
49h
RCR12
35h
02h
Receive control register 1
RCR21
49h
RCR22
35h
03h
Receive control register 2
XCR11
49h
XCR12
35h
04h
Transmit control register 1
XCR21
49h
XCR22
35h
05h
Transmit control register 2
SRGR11
49h
SRGR12
35h
06h
Sample rate generator register 1
SRGR21
49h
SRGR22
35h
07h
Sample rate generator register 2
MCR11
49h
MCR12
35h
08h
Multichannel register 1
MCR21
49h
MCR22
35h
09h
Multichannel register 2
RCERA1
49h
RCERA2
35h
0Ah
Receive channel enable register partition A
RCERB1
49h
RCERA2
35h
0Bh
Receive channel enable register partition B
XCERA1
49h
XCERA2
35h
0Ch
Transmit channel enable register partition A
XCERB1
49h
XCERA2
35h
0Dh
Transmit channel enable register partition B
PCR1
49h
PCR2
35h
0Eh
Pin control register
RCERC1
49h
RCERC2
35h
010h
Additional channel enable register for
128-channel selection
RCERD1
49h
RCERD2
35h
011h
Additional channel enable register for
128-channel selection
XCERC1
49h
XCERC2
35h
012h
Additional channel enable register for
128-channel selection
XCERD1
49h
XCERD2
35h
013h
Additional channel enable register for
128-channel selection
RCERE1
49h
RCERE2
35h
014h
Additional channel enable register for
128-channel selection
RCERF1
49h
RCERF2
35h
015h
Additional channel enable register for
128-channel selection
XCERE1
49h
XCERE2
35h
016h
Additional channel enable register for
128-channel selection
XCERF1
49h
XCERF2
35h
017h
Additional channel enable register for
128-channel selection
RCERG1
49h
RCERG2
35h
018h
Additional channel enable register for
128-channel selection
RCERH1
49h
RCERH2
35h
019h
Additional channel enable register for
128-channel selection
XCERG1
49h
XCERG2
35h
01Ah
Additional channel enable register for
128-channel selection
XCERH1
49h
XCERH2
35h
01Bh
Additional channel enable register for
128-channel selection
38 SGUS035A
April 2003 -- Revised July 2003