SMJ320VC5416HFGW10 Datasheet, PDF (80/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.14.3 McBSP as SPI Master or Slave Timing
Table 5--25 to Table 5--32 assume testing over recommended operating conditions (see Figure 5--24,
Figure 5--25, Figure 5--26, and Figure 5--27).
Table 5--25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)^†
5416-100
MASTER
SLAVE
UNIT
MIN MAX
MIN MAX
t_{su(BDRV-BCKXL)}
t_{h(BCKXL-BDRV)}
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
12
2.2 -- 6P*^‡
ns
4
5 + 12P*^‡
ns
* Not production tested.
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1 / (2 * processor clock)}
Table 5--26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)^†
t_{h(BCKXL-BFXL)}
t_{d(BFXL-BCKXH)}
t_{d(BCKXH-BDXV)}
t_{dis(BCKXL-BDXHZ)}
PARAMETER
Hold time, BFSX low after BCLKX low^¶
Delay time, BFSX low to BCLKX high^#
Delay time, BCLKX high to BDX valid
Disable time, BDX high impedance following last data bit from
BCLKX low
5416-100
MASTER^§
SLAVE
MIN MAX
MIN
MAX
T -- 3* T + 4
C -- 4* C + 3*
-- 4*
5 6P + 2*^‡ 10P + 17^‡
UNIT
ns
ns
ns
C -- 2* C + 3*
ns
t_{dis(BFXH-BDXHZ)}
Disable time, BDX high impedance following last data bit from
BFSX high
2P-- 4*^‡ 6P + 17*^‡ ns
t_d(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4P+ 2*^‡ 8P + 17*^‡ ns
* Not production tested.
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1 / (2 * processor clock)}
§ _{T = BCLKX period = (1 + CLKGDV) * 2P}
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
¶ _{FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX}
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(BCLKX).
BCLKX
BFSX
BDX
BDR
LSB
MSB
t_{h(BCKXL-BFXL)}
t_{d(BFXL-BCKXH)}
Bit 0
Bit 0
t_{dis(BFXH-BDXHZ)}
t_{dis(BCKXL-BDXHZ)}
t_{su(BDRV-BCLXL)}
t_d(BFXL-BDXV)
t_{d(BCKXH-BDXV)}
Bit(n-1)
(n-2)
(n-3)
t_{h(BCKXL-BDRV)}
Bit(n-1)
(n-2)
(n-3)
(n-4)
(n-4)
Figure 5--24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
70 SGUS035A
April 2003 -- Revised July 2003