SMJ320VC5416HFGW10 Datasheet, PDF (36/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
Figure 3--12 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode,
or single memory reads in consecutive mode. The accesses shown in Figure 3--12 always require 3 CLKOUT
cycles to complete.
CLKOUT
A[22:0]
D[15:0]
READ
R/W
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Read
Cycle
Trailing
Cycle
Figure 3--12. Nonconsecutive Memory Read and I/O Read Bus Sequence
26 SGUS035A
April 2003 -- Revised July 2003