SMJ320VC5416HFGW10 Datasheet, PDF (41/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
Data Space (0000 -- 005F)
Hex
0000
001F
Reserved
0020
DRR20
0021
DRR10
0022
DXR20
0023
0024
002F
DXR10
Reserved
0030
DRR22
0031
DRR12
0032
DXR22
0033
DXR12
0034
0035
0036
Reserved
RCERA2
0037
XCERA2
0038
0039
Reserved
003A
RECRA0
003B
XECRA0
003C
003F
0040
0041
Reserved
DRR21
DRR11
0042
DXR21
0043
DXR11
0044
0049
004A
Reserved
RCERA1
004B
XCERA1
004C
005F
Reserved
Data Space
0000
Data Space
(See Breakout)
005F
0060
007F
0080
1FFF
2000
3FFF
4000
5FFF
6000
7FFF
8000
9FFF
A000
BFFF
C000
DFFF
E000
FFFF
Scratch-Pad
RAM
On-Chip
DARAM0
8K Words
On-Chip
DARAM1
8K Words
On-Chip
DARAM2
8K Words
On-Chip
DARAM3
8K Words
On-Chip
DARAM4
8K Words
On-Chip
DARAM5
8K Words
On-Chip
DARAM6
8K Words
On-Chip
DARAM7
8K Words
Hex
0000
FFFF
I/O Space
Reserved
Figure 3--17. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.12.4 DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple DMA
channels that are assigned to the same priority level are handled in a round-robin manner.
3.12.5 DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
3.12.6 DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA reload registers (DMGSA, DMGDA, DMGCR,
and DMGFR). Autoinitialization allows:
• Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfers, but with the reload registers, it can reinitialize these values for
the next block transfer any time after the current block transfer begins.
• Repetitive operation: The CPU does not preload the reload register with new values for each block transfer
but only loads them on the first block transfer.
April 2003 -- Revised July 2003
SGUS035A
31