SMJ320VC5416HFGW10 Datasheet, PDF (84/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.15 Host-Port Interface Timing
5.15.1 HPI8 Mode
Table 5--33 and Table 5--34 assume testing over recommended operating conditions and P = 1 / (2 * processor
clock) (see Figure 5--28 through Figure 5--31). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0,
HCNTL1, and HR/W.
Table 5--33. HPI8 Mode Timing Requirements
t_su(HBV-DSL)
Setup time, HBIL valid before DS low (when HAS is not used), or HBIL valid before HAS
low
t_h(DSL-HBV)
Hold time, HBIL valid after DS low (when HAS is not used), or HBIL valid after HAS low
t_su(HSL-DSL)
t_w(DSL)
t_w(DSH)
t_su(HDV-DSH)
t_h(DSH-HDV)W
Setup time, HAS low before DS low
Pulse duration, DS low
Pulse duration, DS high
Setup time, HD valid before DS high, HPI write
Hold time, HD valid after DS high, HPI write
t_su(GPIO-COH)
t_h(GPIO-COH)
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
* Not production tested.
5416-100
MIN MAX
6
3
8*
13*
7*
3
2
6*
0*
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
74 SGUS035A
April 2003 -- Revised July 2003