SMJ320VC5416HFGW10 Datasheet, PDF (65/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.9 Ready Timing for Externally Generated Wait States
Table 5--14 and Table 5--15 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 5--10, Figure 5--11, Figure 5--12, and Figure 5--13).
Table 5--14. Ready Timing Requirements for Externally Generated Wait States^†
5416-100
MIN
MAX
UNIT
t_su(RDY)
Setup time, READY before CLKOUT low
7
ns
t_h(RDY)
t_v(RDY)MSTRB
t_h(RDY)MSTRB
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low^‡
Hold time, READY after MSTRB low^‡
0
ns
4H -- 6.2* ns
4H*
ns
t_v(RDY)IOSTRB
Valid time, READY after IOSTRB low^‡
4H -- 6* ns
t_h(RDY)IOSTRB
Hold time, READY after IOSTRB low^‡
4H*
ns
* Not production tested.
† _{The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,}
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
‡ _{These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.}
Table 5--15. Ready Switching Characteristics for Externally Generated Wait States^†
PARAMETER
5416-100
MIN MAX
UNIT
t_d(MSCL)
Delay time, CLKOUT low to MSC low
--1*
4 ns
t_d(MSCH)
Delay time, CLKOUT low to MSC high
--1*
4 ns
* Not production tested.
† _{The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,}
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
April 2003 -- Revised July 2003
SGUS035A
55