SMJ320VC5416HFGW10 Datasheet, PDF (62/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.8.2 Memory Write
Table 5--10 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t_c(CO) (see
Figure 5--7).
Table 5--10. Memory Write Switching Characteristics
PARAMETER
t_d(CLKL-A)
t_su(A)MSL
Delay time, CLKOUT low to address valid^†
Setup time, address valid before MSTRB low^†
t_d(CLKL-D)W
Delay time, CLKOUT low to data valid
t_su(D)MSH
Setup time, data valid before MSTRB high
t_h(D)MSH
Hold time, data valid after MSTRB high
t_d(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
t_w(SL)MS
Pulse duration, MSTRB low
t_d(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
* Not production tested.
† _{Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.}
5416-100
MIN
MAX
-- 1*
4
2H -- 3
-- 1*
4
2H -- 5 2H + 6
2H -- 5* 2H + 6*
-- 1*
4
2H -- 3.2*
-- 1*
4*
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
A[22:0]^†
D[15:0]
MSTRB
t_d(CLKL-A)
t_su(A)MSL
t_d(CLKL-D)W
t_d(CLKL-A)
t_su(D)MSH
t_d(CLKL-MSL)
t_w(SL)MS
t_h(D)MSH
t_d(CLKL-MSH)
R/W^†
PS/DS^†
† _{Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.}
Figure 5--7. Memory Write (MSTRB = 0)
52 SGUS035A
April 2003 -- Revised July 2003