SMJ320VC5416HFGW10 Datasheet, PDF (43/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.12.10 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The available
modes are shown in Table 3--11.
Table 3--11. DMA Interrupts
MODE
DINM
IMOD
INTERRUPT
ABU (non-decrement)
1
0
At full buffer only
ABU (non-decrement)
1
1
At half buffer and full buffer
Multiframe
1
0
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
Multiframe
1
1
At end of frame and end of block (DMCTRn = 0)
Either
0
X
No interrupt generated
Either
0
X
No interrupt generated
3.12.11 DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN
bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events
and the DSYN values are shown in Table 3--12.
Table 3--12. DMA Synchronization Events
DSYN VALUE
DMA SYNCHRONIZATION EVENT
0000b
No synchronization used
0001b
McBSP0 receive event
0010b
McBSP0 transmit event
0011b
McBSP2 receive event
0100b
McBSP2 transmit event
0101b
McBSP1 receive event
0110b
McBSP1 transmit event
0111b
McBSP0 receive event -- ABIS mode
1000b
McBSP0 transmit event -- ABIS mode
1001b
McBSP2 receive event -- ABIS mode
1010b
McBSP2 transmit event -- ABIS mode
1011b
McBSP1 receive event -- ABIS mode
1100b
McBSP1 transmit event -- ABIS mode
1101b
Timer interrupt event
1110b
INT3 goes active
1111b
Reserved
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the
number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.
DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When
the 5416 is reset, the interrupts from these three DMA channels are deselected. The INTSEL bit field in the
DMPREC register can be used to select these interrupts, as shown in Table 3--13.
Table 3--13. DMA Channel Interrupt Selection
INTSEL Value
00b (reset)
01b
IMR/IFR[6]
BRINT2
BRINT2
IMR/IFR[7]
BXINT2
BXINT2
IMR/IFR[10]
BRINT1
DMAC2
IMR/IFR[11]
BXINT1
DMAC3
10b
DMAC0
DMAC1
DMAC2
DMAC3
11b
Reserved
April 2003 -- Revised July 2003
SGUS035A
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