SMJ320VC5416HFGW10 Datasheet, PDF (47/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
Table 3--15. Peripheral Memory-Mapped Registers for Each DSP Subsystem
NAME
DRR20
DRR10
DXR20
DXR10
TIM
PRD
TCR
—
SWWSR
BSCR
—
SWCR
HPIC
—
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
—
SPSA0
SPSD0
—
GPIOCR
GPIOSR
CSIDR
—
DRR21
DRR11
DXR21
DXR11
—
SPSA1
SPSD1
—
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
—
ADDRESS
DEC
HEX
32
20
33
21
34
22
35
23
36
24
37
25
38
26
39
27
40
28
41
29
42
2A
43
2B
44
2C
45--47 2D--2F
48
30
49
31
50
32
51
33
52
34
53
35
54--55
36--37
56
38
57
39
58--59 3A--3B
60
3C
61
3D
62
3E
63
3F
64
40
65
41
66
42
67
43
68--71
44--47
72
48
73
49
74--83
4A--53
84
54
85
55
86
56
87
57
88
58
89--95
59--5F
DESCRIPTION
McBSP 0 Data Receive Register 2
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer Register
Timer Period Register
Timer Control Register
Reserved
Software Wait-State Register
Bank-Switching Control Register
Reserved
Software Wait-State Control Register
HPI Control Register (HMODE = 0 only)
Reserved
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
McBSP 2 Subbank Address Register^†
McBSP 2 Subbank Data Register^†
Reserved
McBSP 0 Subbank Address Register^†
McBSP 0 Subbank Data Register^†
Reserved
General-Purpose I/O Control Register
General-Purpose I/O Status Register
Device ID Register
Reserved
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
Reserved
McBSP 1 Subbank Address Register^†
McBSP 1 Subbank Data Register^†
Reserved
DMA Priority and Enable Control Register
DMA Subbank Address Register^‡
DMA Subbank Data Register with Autoincrement^‡
DMA Subbank Data Register^‡
Clock Mode Register (CLKMD)
Reserved
† _{See Table 3--16 for a detailed description of the McBSP control registers and their subaddresses.}
‡ _{See Table 3--17 for a detailed description of the DMA subbank addressed registers.}
April 2003 -- Revised July 2003
SGUS035A
37