SMJ320VC5416HFGW10 Datasheet, PDF (74/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.12 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 5--19 assumes testing over recommended operating conditions and H = 0.5t_c(CO) (see Figure 5--18).
Table 5--19. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
PARAMETER
5416-100
MIN MAX
UNIT
t_d(CLKL-IAQL)
Delay time, CLKOUT low to IAQ low
t_d(CLKL-IAQH)
Delay time, CLKOUT low to IAQ high
t_{d(CLKL-IACKL)}
Delay time, CLKOUT low to IACK low
t_{d(CLKL-IACKH)}
Delay time, CLKOUT low to IACK high
t_d(CLKL-A)
Delay time, CLKOUT low to address valid
t_w(IAQL)
Pulse duration, IAQ low
t_w(IACKL)
Pulse duration, IACK low
* Not production tested.
-- 1*
-- 1*
-- 1.2*
-- 1*
-- 1*
2H -- 2*
2H -- 3*
4 ns
4 ns
4 ns
4 ns
4 ns
ns
ns
CLKOUT
A[22:0]
t_{d(CLKL -- IAQL)}
t_d(CLKL--A)
t_d(CLKL--A)
t_{d(CLKL -- IAQH)}
IAQ
t_w(IAQL)
t_{d(CLKL -- IACKL)}
t_{d(CLKL -- IACKH)}
IACK
t_w(IACKL)
Figure 5--18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
64 SGUS035A
April 2003 -- Revised July 2003