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SMJ320VC5416HFGW10 Datasheet, PDF (85/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor | |||
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Electrical Specifications
Table 5--34. HPI8 Mode Switching Characteristics
PARAMETER
5416-100
MIN
MAX
UNIT
ten(DSL-HD)
Enable time, HD driven from DS low
0*
10*
ns
Case 1a: Memory accesses when DMAC is active
in 32-bit mode and tw(DSH) < 36Pâ
36P+10--tw(DSH)*
Case 1b: Memory accesses when DMAC is active
in 32-bit mode and tw(DSH) ⥠36Pâ
10*
td(DSL-HDV1)
Delay time, DS low to HD
valid for first byte of an HPI
read
Case 1c: Memory accesses when DMAC is active
in 16-bit mode and tw(DSH) < I8Pâ
Case 1d: Memory accesses when DMAC is active
in 16-bit mode and tw(DSH) ⥠I8Pâ
18P+10--tw(DSH)*
10*
ns
Case 2a: Memory accesses when DMAC is inactive
and tw(DSH) < 10Pâ
10P+10--tw(DSH)*
Case 2b: Memory accesses when DMAC is inactive
and tw(DSH) ⥠10Pâ
10*
Case 3: Register accesses
10*
td(DSL-HDV2) Delay time, DS low to HD valid for second byte of an HPI read
th(DSH-HDV)R Hold time, HD valid after DS high, for a HPI read
0*
tv(HYH-HDV)
Valid time, HD valid after HRDY high
td(DSH-HYL)
Delay time, DS high to HRDY lowâ¡
Case 1a: Memory accesses when DMAC is active
in 16-bit modeâ
10*
ns
ns
2*
ns
8*
ns
18P+6*
td(DSH-HYH)
Delay time, DS high to HRDY Case 1b: Memory accesses when DMAC is active
highâ¡
in 32-bit modeâ
Case 2: Memory accesses when DMAC is inactiveâ
Case 3: Write accesses to HPIC register§
36P+6*
ns
10P+6*
6P+6*
td(HCS-HRDY)
td(COH-HYH)
td(COH-HTX)
td(COH-GPIO)
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output
6*
ns
9
ns
6
ns
5*
ns
* Not production tested.
â DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times
are affected by DMAC activity.
â¡ The HRDY output is always high when the HCS input is high, regardless of DS timings.
§ This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronously,
and do not cause HRDY to be deasserted.
April 2003 -- Revised July 2003
SGUS035A
75
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