SMJ320VC5416HFGW10 Datasheet, PDF (45/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.14 Device ID Register
A read-only memory-mapped register has been added to the 5416 to allow user application software to identify
on which device the program is being executed.
15--8
7
4
3
0
Chip ID
Chip Revision
SUBSYSID
R
R
R
Bits 15:8: Chip_ID (hex code of 16)
Bits 7:4: Chip_Revision ID
Bits 3:0: Subsystem_ID (0000b for single core device)
Figure 3--21. Device ID Register (CSIDR) [MMR Address 003Eh]
3.15 Memory-Mapped Registers
The 5416 has 27 memory-mapped CPU registers, which are mapped in data memory space address 0h to
1Fh. Each 5416 device also has a set of memory-mapped registers associated with peripherals. Table 3--14
gives a list of CPU memory-mapped registers (MMRs) available on 5416. Table 3--15 shows additional
peripheral MMRs associated with the 5416.
NAME
IMR
IFR
—
ST0
ST1
AL
AH
AG
BL
BH
BG
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
BK
BRC
RSA
Table 3--14. CPU Memory-Mapped Registers
DEC
0
1
2--5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
ADDRESS
HEX
0
1
2--5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
DESCRIPTION
Interrupt mask register
Interrupt flag register
Reserved for testing
Status register 0
Status register 1
Accumulator A low word (15--0)
Accumulator A high word (31--16)
Accumulator A guard bits (39--32)
Accumulator B low word (15--0)
Accumulator B high word (31--16)
Accumulator B guard bits (39--32)
Temporary register
Transition register
Auxiliary register 0
Auxiliary register 1
Auxiliary register 2
Auxiliary register 3
Auxiliary register 4
Auxiliary register 5
Auxiliary register 6
Auxiliary register 7
Stack pointer register
Circular buffer size register
Block repeat counter
Block repeat start address
April 2003 -- Revised July 2003
SGUS035A
35