SMJ320VC5416HFGW10 Datasheet, PDF (26/96 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.6.1 Software-Programmable Wait-State Generator
The software wait-state generator of the 5416 can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line.
When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator
are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of
the 5416.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is
initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown
in Figure 3--5 and described in Table 3--3.
15
XPA
R/W-0
14
12
I/O
R/W-111
11
9
Data
R/W-111
8
6
Data
R/W-111
5
3
Program
R/W-111
2
0
Program
R/W-111
LEGEND: R=Read, W=Write, 0=Value after reset
Figure 3--5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
BIT
NO.
NAME
15
XPA
14--12
I/O
11--9
Data
8--6
Data
5--3
Program
2--0
Program
Table 3--3. Software Wait-State Register (SWWSR) Bit Fields
RESET
VALUE
FUNCTION
0
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for program space wait states.
I/O space. The field value (0--7) corresponds to the base number of wait states for I/O space accesses
111 within addresses 0000--FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
Upper data space. The field value (0--7) corresponds to the base number of wait states for external
111 data space accesses within addresses 8000--FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Lower data space. The field value (0--7) corresponds to the base number of wait states for external
111 data space accesses within addresses 0000--7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Upper program space. The field value (0--7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
111 ^{- XPA = 0: xx8000 -- xxFFFFh}
- XPA = 1: 400000h -- 7FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Program space. The field value (0--7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
111 ^{- XPA = 0: xx0000 -- xx7FFFh}
- XPA = 1: 000000 -- 3FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
16 SGUS035A
April 2003 -- Revised July 2003