LM3S5762 Datasheet, PDF (83/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Stellaris® LM3S5762 Microcontroller
2.5.3
2.5.4
Table 2-9. Interrupts (continued)
Vector Number
38
39
40
41-43
44
45
46-54
55
56-58
59
60
61
62
63
Interrupt Number (Bit
in Interrupt Registers)
22
23
24
25-27
28
29
30-38
39
40-42
43
44
45
46
47
Vector Address or
Offset
0x0000.0098
0x0000.009C
0x0000.00A0
-
0x0000.00B0
0x0000.00B4
-
0x0000.00DC
-
0x0000.00EC
0x0000.00F0
-
0x0000.00F8
0x0000.00FC
Description
Timer 1B
Timer 2A
Timer 2B
Reserved
System Control
Flash Memory Control
Reserved
CAN0
Reserved
Hibernation Module
USB
Reserved
µDMA Software
µDMA Error
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 81. Figure 2-6 on page 84 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
November 17, 2011
83
Texas Instruments-Production Data