LM3S5762 Datasheet, PDF (24/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Table of Contents
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USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 .............................. 700
USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 .............................. 700
USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 .............................. 700
USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A ................... 701
USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A ................... 701
USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A ................... 701
USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B ....................... 702
USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B ....................... 702
USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B ....................... 702
USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ................... 703
USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ................... 703
USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C ................... 703
USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D ............. 704
USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D ............ 704
USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D ............ 704
USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset
0x304 ........................................................................................................................... 705
USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset
0x308 ........................................................................................................................... 705
USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset
0x30C ........................................................................................................................... 705
USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ............. 706
USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 ............ 707
USB External Power Control (USBEPC), offset 0x400 ...................................................... 708
USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 ................. 711
USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 ............................ 712
USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C ......... 713
USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 ............................ 714
USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 ....................................... 715
USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 .................... 716
USB General-Purpose Control and Status (USBGPCS), offset 0x41C ............................... 717
Pulse Width Modulator (PWM) .................................................................................................... 718
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 729
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 730
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 731
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 732
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 733
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 734
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 735
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 736
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 737
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 738
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 738
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 738
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 741
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 741
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 741
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 744
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November 17, 2011
Texas Instruments-Production Data