LM3S5762 Datasheet, PDF (420/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

General-Purpose Timers
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
12
reserved
RO
RO
RO
0
0
0
11
10
9
8
7
CBEMIS CBMMIS TBTOMIS
RO
RO
RO
RO
RO
0
0
0
0
0
22
21
RO
RO
0
0
6
5
reserved
RO
RO
0
0
20
19
18
17
16
RO
RO
RO
RO
RO
0
0
0
0
0
4
3
2
1
0
RTCMIS CAEMIS CAMMIS TATOMIS
RO
RO
RO
RO
RO
0
0
0
0
0
Bit/Field
31:11
10
9
8
7:4
3
2
1
0
Name
reserved
CBEMIS
CBMMIS
TBTOMIS
reserved
RTCMIS
CAEMIS
CAMMIS
TATOMIS
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0x00
0
0
0
0x0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
420
November 17, 2011
Texas Instruments-Production Data