LM3S5762 Datasheet, PDF (21/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Stellaris® LM3S5762 Microcontroller
Register 13:
Register 14:
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Register 25:
Register 26:
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 519
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 521
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 522
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 523
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 524
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 525
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 526
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 527
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 528
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 529
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 530
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 531
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 532
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 533
Synchronous Serial Interface (SSI) ............................................................................................ 534
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 548
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 550
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 552
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 553
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 555
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 556
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 558
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 559
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 560
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 561
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 562
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 563
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 564
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 565
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 566
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 567
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 568
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 569
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 570
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 571
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 572
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 573
Controller Area Network (CAN) Module ..................................................................................... 574
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 595
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 597
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 599
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 600
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 601
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 602
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 604
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 605
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 605
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 606
November 17, 2011
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