LM3S5762 Datasheet, PDF (236/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

System Control
Register 33: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
TIMER2 TIMER1 TIMER0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SSI0
reserved
UART0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:19
18
17
16
15:5
4
3:1
0
Name
reserved
TIMER2
TIMER1
TIMER0
reserved
SSI0
reserved
UART0
Type
RO
R/W
R/W
R/W
RO
R/W
RO
R/W
Reset
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Timer 2 Reset Control. Reset control for General-Purpose Timer module
2.
Timer 1 Reset Control. Reset control for General-Purpose Timer module
1.
Timer 0 Reset Control. Reset control for General-Purpose Timer module
0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI0 Reset Control. Reset control for SSI unit 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART0 Reset Control. Reset control for UART unit 0.
236
November 17, 2011
Texas Instruments-Production Data