LM3S5762 Datasheet, PDF (290/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Micro Direct Memory Access (μDMA)
8.1
8.2
Block Diagram
Figure 8-1. μDMA Block Diagram
DMA error
μDMA
Controller
Peripheral
request
DMA Channel 0 ^done
•
•
•
request
Peripheral
DMA Channel N-1 ^done
Nested
Vectored
Interrupt
IRQ
Controller
(NVIC)
General
Peripheral N
Registers
request
done
DMASTAT
DMACFG
DMACTLBASE
DMAALTBASE
DMAWAITSTAT
DMASWREQ
DMAUSEBURSTSET
DMAUSEBURSTCLR
DMAREQMASKSET
DMAREQMASKCLR
DMAENASET
DMAENACLR
DMAALTSET
DMAALTCLR
DMAPRIOSET
DMAPRIOCLR
DMAERRCLR
ARM
Cortex-M3
System Memory
CH Control Table
DMASRCENDP
DMADSTENDP
DMACHCTRL
•
•
•
DMASRCENDP
DMADSTENDP
DMACHCTRL
Transfer Buffers
Used by uDMA
Functional Description
The μDMA controller is a flexible and highly configurable DMA controller designed to work effeciently
with the microcontroller's Cortex-M3 processor core. It supports multiple data sizes and address
increment schemes, multiple levels of priority among DMA channels, and several transfer modes
to allow for sophisticated programmed data transfers. The DMA controller's usage of the bus is
always subordinate to the processor core, and so it will never hold up a bus transaction by the
processor. Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer
bandwidth it provides is essentially free, with no impact on the rest of the system. The bus architecture
has been optimized to greatly reduce contention between the processor core and the μDMA controller,
thus improving performance. The optimizations include RAM striping and peripheral bus segmentation,
which in many cases allows both the processor core and the μDMA controller to access the bus
and perform simultaneous data transfers.
Each peripheral function that is supported has a dedicated channel on the μDMA controller that can
be configured independently.
The μDMA controller makes use of a unique configuration method by using channel control structures
that are maintained in system memory by the processor. While simple transfer modes are supported,
it is also possible to build up sophisticated "task" lists in memory that allow the controller to perform
arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The
controller also supports the use of ping-pong buffering to accomodate constant streaming of data
to or from a peripheral.
Each channel also has a configurable arbitration size. The arbitration size is the number of items
that will be transferred in a burst before the controller rearbitrates for channel priority. Using the
arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral
each time it makes a DMA service request.
290
November 17, 2011
Texas Instruments-Production Data