LM3S5762 Datasheet, PDF (309/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Stellaris® LM3S5762 Microcontroller
a. Process the newly received data in buffer A, or signal the buffer processing code that buffer
A has data available.
b. Reprogram the primary channel control word at offset 0x88 according to Table
8-12 on page 308.
2. Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the
field is 0, this means buffer B is complete. If buffer B is complete, then:
a. Process the newly received data in buffer B, or signal the buffer processing code that buffer
B has data available.
b. Reprogram the alternate channel control word at offset 0x288 according to Table
8-12 on page 308.
8.4 Register Map
Table 8-13 on page 309 lists the μDMA channel control structures and registers. The channel control
structure shows the layout of one entry in the channel control table. The channel control table is
located in system memory, and the location is determined by the application, that is, the base
address is n/a (not applicable). In the table below, the offset for the channel control structures is the
offset from the entry in the channel control table. See “Channel Configuration” on page 292 and Table
8-3 on page 293 for a description of how the entries in the channel control table are located in memory.
The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base
address of 0x400F.F000. Note that the μDMA module clock must be enabled before the registers
can be programmed (see page 229). There must be a delay of 3 system clocks after the μDMA
module clock is enabled before any μDMA module registers are accessed.
Table 8-13. μDMA Register Map
Offset Name
Type
μDMA Channel Control Structure
0x000 DMASRCENDP
R/W
0x004 DMADSTENDP
R/W
0x008 DMACHCTL
R/W
μDMA Registers
0x000 DMASTAT
RO
0x004 DMACFG
WO
0x008 DMACTLBASE
R/W
0x00C DMAALTBASE
RO
0x010 DMAWAITSTAT
RO
0x014 DMASWREQ
WO
0x018 DMAUSEBURSTSET R/W
0x01C DMAUSEBURSTCLR
WO
0x020 DMAREQMASKSET
R/W
Reset
Description
-
DMA Channel Source Address End Pointer
-
DMA Channel Destination Address End Pointer
-
DMA Channel Control Word
0x001F.0000
-
0x0000.0000
0x0000.0200
0x0000.0000
-
0x0000.0000
-
0x0000.0000
DMA Status
DMA Configuration
DMA Channel Control Base Pointer
DMA Alternate Channel Control Base Pointer
DMA Channel Wait on Request Status
DMA Channel Software Request
DMA Channel Useburst Set
DMA Channel Useburst Clear
DMA Channel Request Mask Set
See
page
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November 17, 2011
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