LM3S5762 Datasheet, PDF (353/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Stellaris® LM3S5762 Microcontroller
Table 9-3. GPIO Signals (64LQFP) (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
PE2
2
I/O
TTL
GPIO port E bit 2.
PE3
1
I/O
TTL
GPIO port E bit 3.
PE4
8
I/O
TTL
GPIO port E bit 4.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
9.2 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the four JTAG/SWD pins (PC[3:0]). The
JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1
and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins
back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block(see Figure
9-1 on page 353 and Figure 9-2 on page 354). The LM3S5762 microcontroller contains five ports and
thus five of these physical GPIO blocks.
Figure 9-1. Digital I/O Pads
Commit
Control
GPIOLOCK
GPIOCR
Alternate Input
Alternate Output
Alternate output Enable
Mode
Control
GPIOAFSEL
Pad Input
Data
Control
GPIODATA
GPIODIR
GPIO Input
GPIO Output
GPIO Output Enable
Pad Output
Pad Output
Enable
Digital
I/O
Pad
Package I/O Pin
Interrupt
Interrupt
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Pad
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
November 17, 2011
353
Texas Instruments-Production Data