LM3S5762 Datasheet, PDF (545/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Stellaris® LM3S5762 Microcontroller
Figure 14-12 on page 545 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
t_Setup=(2*t_SSIClk)
t_Hold=t_SSIClk
SSIClk
SSIFss
14.3.5
14.4
SSIRx
First RX data to be
sampled by SSI slave
DMA Operation
The SSI peripheral provides an interface connected to the μDMA controller. The DMA operation of
the SSI is enabled through the SSI DMA Control (SSIDMACTL) register. When DMA operation is
enabled, the SSI will assert a DMA request on the receive or transmit channel when the associated
FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever
there is any data in the receive FIFO. A burst transfer request is asserted whenever the amount of
data in the receive FIFO is 4 or more items. For the transmit channel, a single transfer request is
asserted whenever there is at least one empty location in the transmit FIFO. The burst request is
asserted whenever the transmit FIFO has 4 or more empty slots. The single and burst DMA transfer
requests are handled automatically by the μDMA controller depending how the DMA channel is
configured. To enable DMA operation for the receive channel, the RXDMAE bit of the DMA Control
(SSIDMACTL) register should be set. To enable DMA operation for the transmit channel, the TXDMAE
bit of SSIDMACTL should be set. If DMA is enabled, then the μDMA controller will trigger an interrupt
when a transfer is complete. The interrupt will occur on the SSI interrupt vector. Therefore, if interrupts
are used for SSI operation and DMA is enabled, the SSI interrupt handler must be designed to
handle the μDMA completion interrupt.
See “Micro Direct Memory Access (μDMA)” on page 289 for more details about programming the
μDMA controller.
Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
November 17, 2011
545
Texas Instruments-Production Data