LM3S5762 Datasheet, PDF (16/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Table of Contents
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 119
Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 119
Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 119
Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 121
CPU ID Base (CPUID), offset 0xD00 ............................................................................... 122
Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 123
Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 126
Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 127
System Control (SYSCTRL), offset 0xD10 ....................................................................... 129
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 131
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 133
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 134
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 135
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 136
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 140
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 146
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 147
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 148
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 149
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 150
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 152
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 153
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 153
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 153
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 153
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 155
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 155
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 155
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 155
System Control ............................................................................................................................ 170
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 185
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 187
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 188
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 189
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 190
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 191
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 192
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 193
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 197
Register 10: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 198
Register 11: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 200
Register 12: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 202
Register 13: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 203
Register 14: Device Identification 1 (DID1), offset 0x004 ..................................................................... 204
Register 15: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 206
Register 16: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 207
Register 17: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 209
Register 18: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 210
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November 17, 2011
Texas Instruments-Production Data