LM3S5762 Datasheet, PDF (207/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Stellaris® LM3S5762 Microcontroller
Register 16: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. The PWM, SARADC0,
MAXADCSPD, WDT, SWO, SWD, and JTAG bits mask the RCGC0, SCGC0, and DCGC0 registers.
Other bits are passed as 0. MAXADCSPD is clipped to the maximum value specified in DC1.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0111.32FF
31
30
29
28
reserved
Type RO
RO
RO
RO
Reset
0
0
0
0
15
14
13
12
MINSYSDIV
Type RO
RO
RO
RO
Reset
0
0
1
1
27
26
RO
RO
0
0
11
10
reserved
RO
RO
0
0
25
24
CAN0
RO
RO
0
1
9
8
MAXADCSPD
RO
RO
1
0
23
22
21
reserved
RO
RO
RO
0
0
0
20
PWM
RO
1
7
MPU
RO
1
6
5
4
HIB TEMPSNS PLL
RO
RO
RO
1
1
1
19
18
17
reserved
RO
RO
RO
0
0
0
3
WDT
RO
1
2
SWO
RO
1
1
SWD
RO
1
16
ADC
RO
1
0
JTAG
RO
1
Bit/Field
31:25
24
23:21
20
19:17
16
15:12
Name
reserved
CAN0
reserved
PWM
reserved
ADC
MINSYSDIV
Type
RO
RO
RO
RO
RO
RO
RO
Reset
0
1
0
1
0
1
0x3
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Module Present
When set, indicates that the PWM module is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Module Present. When set, indicates that the ADC module is
present.
System Clock Divider. Minimum 4-bit divider value for system clock.
The reset value is hardware-dependent. See the RCC register for how
to change the system clock divisor using the SYSDIV bit.
Value Description
0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.
11:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
November 17, 2011
207
Texas Instruments-Production Data