LM3S5762 Datasheet, PDF (351/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Stellaris® LM3S5762 Microcontroller
alternate hardware functions are enabled by setting the appropriate bit in the GPIO Alternate
Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the
GPIO Port Control (GPIOPCTL) register to the numeric enoding shown in the table below. Note
that each pin must be programmed individually; no type of grouping is implied by the columns in
the table.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting
RST puts the pins back to their default state.
Table 9-1. GPIO Pins With Non-Zero Reset Values
GPIO Pins
PA[1:0]
PA[5:2]
PC[3:0]
Default State
UART0
SSI0
JTAG/SWD
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
0
1
1
0
0
1
1
0
1
GPIOPCTL
0x1
0x1
0x3
Table 9-2. GPIO Pins and Alternate Functions (64LQFP)
IO
Pin Number
Multiplexed Function
PA0
17
U0Rx
PA1
18
U0Tx
PA2
19
SSI0Clk
PA3
20
SSI0Fss
PA4
21
SSI0Rx
PA5
22
SSI0Tx
PA6
25
PWM4
PA7
26
PWM5
PB0
41
USB0ID
PB1
42
USB0VBUS
PB2
47
CCP0
PB3
27
Fault0
PB4
58
CAN0Rx
PB5
57
CAN0Tx
PB6
56
CCP1
PB7
55
NMI
PC0
52
TCK
PC1
51
TMS
PC2
50
TDI
PC3
49
TDO
PC4
11
CCP2
PC5
14
USB0EPEN
PC6
15
USB0PFLT
PC7
16
CCP4
PD0
61
PWM0
Multiplexed Function
SWCLK
SWDIO
SWO
November 17, 2011
351
Texas Instruments-Production Data