LM3S5762 Datasheet, PDF (759/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Stellaris® LM3S5762 Microcontroller
Register 49: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074
Register 50: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4
Register 51: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4
This register specifies which fault pin inputs are used to indicate a fault condition. Each bit in the
following register indicates whether the corresponding fault pin is included in the fault condition. All
enabled fault pins are ORed together to form the PWMnFLTSRC0 portion of the fault condition.
The PWMnFLTSRC0 fault condition is then ORed with the PWMnFLTSRC1 fault condition to
generate the final fault condition for the PWM generator.
PWM0 Fault Source 0 (PWM0FLTSRC0)
Base 0x4002.8000
Offset 0x074
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FAULT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
FAULT0
Type
RO
R/W
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault0
Specifies the contribution of the FAULT0 input to the generation of a
fault condition.
Value Description
0 Suppressed
The FAULT0 signal is suppressed and cannot generate a fault
condition.
1 Generated
The FAULT0 signal value is ORed with all other fault condition
generation inputs (Fault signals).
November 17, 2011
759
Texas Instruments-Production Data