LM3S5762 Datasheet, PDF (302/841 Pages) Texas Instruments – Stellaris® LM3S5762 Microcontroller

Micro Direct Memory Access (μDMA)
8.2.7
8.2.8
8.2.9
Transfer Size and Increment
The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination
data size must be the same for any given transfer. The source and destination address can be
auto-incremented by bytes, half-words, or words, or can be set to no increment. The source and
destination address increment values can be set independently, and it is not necessary for the
address increment to match the data size as long as the increment is the same or larger than the
data size. For example, it is possible to perform a transfer using 8-bit data size, but using an address
increment of full words (4 bytes). The data to be transferred must be aligned in memory according
to the data size (8, 16, or 32 bits).
Table 8-5 on page 302 shows the configuration to read from a peripheral that supplies 8-bit data.
Table 8-5. μDMA Read Example: 8-Bit Peripheral
Field
Source data size
Destination data size
Source address increment
Destination address increment
Source end pointer
Destination end pointer
Configuration
8 bits
8 bits
No increment
Byte
Peripheral read FIFO register
End of the data buffer in memory
Peripheral Interface
Each peripheral that supports μDMA has a DMA single request and/or burst request signal that is
asserted when the device is ready to transfer data. The request signal can be disabled or enabled
by using the DMA Channel Request Mask Set (DMAREQMASKSET) and DMA Channel Request
Mask Clear (DMAREQMASKCLR) registers. The DMA request signal is disabled, or masked, when
the channel request mask bit is set. When the request is not masked, the DMA channel is configured
correctly and enabled, and the peripheral asserts the DMA request signal, the μDMA controller will
begin the transfer.
When a DMA transfer is complete, the μDMA controller asserts a DMA Done signal, which is routed
through the interrupt vector of the peripheral. Therefore, if DMA is used to transfer data for a
peripheral and interrupts are used, then the interrupt handler for that peripheral must be designed
to handle the μDMA transfer completion interrupt. When DMA is enabled for a peripheral, the μDMA
controller will mask the normal interrupts for a peripheral. This means that when a large amount of
data is transferred using DMA, instead of receiving multiple interrupts from the peripheral as data
flows, the processor will only receive one interrupt when the transfer is complete.
The interrupt request from the μDMA controller is automatically cleared when the interrupt handler
is activated.
Software Request
There is a dedicated μDMA channel for software-initiated transfers. This channel also has a dedicated
interrupt to signal completion of a DMA transfer. A transfer is initiated by software by first configuring
and enabling the transfer, and then issuing a software request using the DMA Channel Software
Request (DMASWREQ) register. For software-based transfers, the Auto transfer mode should be
used.
It is possible to initiate a transfer on any channel using the DMASWREQ register. If a request is
initiated by software using a peripheral DMA channel, then the completion interrupt will occur on
the interrupt vector for the peripheral instead of the software interrupt vector. This means that any
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November 17, 2011
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